From: Alexandre Oliva (oliva@dcc.unicamp.br)
Date: Wed Dec 09 1998 - 06:18:16 EST
On Dec 7, 1998, Godmar Back <gback@cs.utah.edu> wrote:
>> > I already mentioned one possible reason: the non-alignment of branch targets.
>> Yep, it may cause large differences WRT to internal caches of the
>> processors too.
> The alignment issue seems like it should be easy to fix.
> What do you think?
Dunno. Isn't the code already aligned at 8-byte boundaries, due to
gc_alloc() for the JIT?
BTW, I've just got this URL from the EGCS mailing list. It contains
lots of hints for optimizing code for Pentium* processors.
http://www.announce.com/agner/assem/
--
Alexandre Oliva http://www.dcc.unicamp.br/~oliva aoliva@{acm.org}
oliva@{dcc.unicamp.br,gnu.org,egcs.cygnus.com,samba.org}
Universidade Estadual de Campinas, SP, Brasil
This archive was generated by hypermail 2b29 : Sat Sep 23 2000 - 19:57:08 EDT